Title :
New features in synchronous FIFOs
Author_Institution :
Paradigm Technol. Inc., San Jose, CA, USA
Abstract :
First in first out (FIFO) buffers are widely used by designers to improve system speed and functionality while reducing part count and cost. The synchronous FIFO introduces a new FIFO architecture to provide improved performance and ease of use in system designs. The synchronous architecture has all of the capability of the prior asynchronous types with the advantages of higher speed, a simpler interface and better timing margins. Also, new FIFO features have been introduced with the change to synchronous architecture. These features make the new families of synchronous FIFOs increasingly valuable in systems design. As a result, synchronous FIFOs are rapidly replacing asynchronous types in all applications
Keywords :
buffer storage; cellular arrays; integrated memory circuits; memory architecture; timing; FIFO architecture; FIFO buffers; functionality; synchronous FIFOs; system designs; system speed; timing margins; Clocks; Control systems; Cost function; Counting circuits; Damping; Data buses; Logic arrays; Read-write memory; Resistors; Timing;
Conference_Titel :
WESCON/'93. Conference Record,
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9970-6
DOI :
10.1109/WESCON.1993.488598
