An effective fault-tolerant technique for circular butterfly parallel systems

The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI/WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures. A resulting butterfly system with L levels involves (1/log₂L)% spare PEs and roughly 50% additional links. Reconfiguration in response fault is easy and can be performed in a distributed manner. The analytic results show that the proposed design exhibits significantly improved reliability