DocumentCode :
3270773
Title :
METASIS: A meta heuristic based logic optimizer
Author :
Ranjan, Gyan ; Kumar, Pankaj ; Gupta, Prosenjit
Author_Institution :
Infosys Tech. Ltd. Bangalore, Bangalore
fYear :
2007
fDate :
5-8 Aug. 2007
Firstpage :
1501
Lastpage :
1504
Abstract :
In this paper, we describe METASIS, a metaheuristic based logic optimizer that uses SIS operators as black box procedures. This provides an automatic capability for generation of scripts for logic optimization as opposed to using empirical scripts. The tool uses SIS commands to traverse the state space of equivalent logic networks and identifies a good sequence of commands to optimize the given logic network. Experimental comparisons of the different approaches with the empirical rugged script, available with the SIS distribution, are reported.
Keywords :
circuit optimisation; equivalent circuits; logic circuits; logic design; METASIS; SIS operator; equivalent logic network; metaheuristic based logic optimizer; sequential interactive synthesis system; Automatic logic units; Circuit synthesis; Combinational circuits; Data structures; Information technology; Latches; Logic circuits; Network synthesis; Optimization methods; Space technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
ISSN :
1548-3746
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2007.4488825
Filename :
4488825
Link To Document :
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