A new scheduling algorithm for processor-based logic emulation systems

In this paper a design compilation CAD tool suite, that maps gate-level netlists of design-under-test (DUT) into a specific class of processor-based logic emulation systems, is presented. The application of static scheduling algorithms and their effect on logic emulation time is discussed. A variation of static scheduling algorithm, and its enhancement, are introduced and results on ten MCNC benchmark circuits are presented and compared. Our results show that both algorithms result in an average processor workload of more than 83% while keeping processor idle time close to minimal. Also, the execution speed-up achieved by both algorithms, on average, is 50 times faster than sequential execution of emulation program.