Partitioning exploration for automated mapping of discrete cosine transforms onto distributed hardware architectures

A high-level partitioning methodology has been reported which explores the space of equivalent discrete Fourier transform formulations, achieving significant improvements over previously published results. In this article, we discuss the extension of this formulation-exploration strategy to partition the discrete cosine transform (DCT) onto distributed hardware architectures, e.g. multi-FPGA platforms. We study several regular DCT formulations and consider their potential for distributed implementation. By analyzing the DCT computational structure, a new Cooley-Tukey-like formulation was derived which allows the DCT factorization into arbitrary sized blocks while preserving structural regularity. Experiments were conducted to measure the partition quality of the previous and new DCT formulations, evidencing the need for formulation-exploration as part of the partition optimization process.