DocumentCode :
3270849
Title :
A parallel architecture for data compression
Author :
Henriques, Selwyn ; Ranganathan, N.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear :
1990
fDate :
9-13 Dec 1990
Firstpage :
260
Lastpage :
266
Abstract :
The authors describe a parallel algorithm and architecture for implementing the LZ technique for data compression. Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. The LZ-based compression method is a very powerful technique and gives very high compression efficiency for text as well as image data. The proposed architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n2 to n. The data compression hardware can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. The basic processor cell for the systolic array is currently being implemented using CMOS VLSI technology
Keywords :
VLSI; data compression; parallel algorithms; parallel architectures; systolic arrays; CMOS VLSI; LZ technique; LZ-based compression; buffer selection; compression efficiency; data compression; image data; parallel algorithm; parallel architecture; parallelism; pipelining; text; CMOS technology; Computer architecture; Costs; Data compression; Image coding; Parallel algorithms; Parallel architectures; Parallel processing; Pipeline processing; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2087-0
Type :
conf
DOI :
10.1109/SPDP.1990.143545
Filename :
143545
Link To Document :
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