Title :
A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 /spl mu/m logic process
Author :
Gillingham, P. ; Hold, B. ; Mes, I. ; O´Connell, C. ; Schofield, P. ; Skjaveland, K. ; Torrance, R. ; Wojcicki, T. ; Chow, H.
Author_Institution :
MOSAID Technol. Inc., Carp, Ont., Canada
Abstract :
This 256 k DRAM macrocell in a 0.8 /spl mu/m single-poly, double-metal, p-substrate, n-well logic process offers 3 times the density of an embedded SRAM without special processing steps. Robust data retention and soft-error performance are achieved by use of a p-channel 1T cell featuring a flexible high-bandwidth interface to support a variety of applications. Three macrocells are used for a 768 k queue memory in a 1.244 Gb/s ATM switch ASIC.
Keywords :
DRAM chips; application specific integrated circuits; asynchronous transfer mode; cellular arrays; electronic switching systems; real-time systems; 0.8 micron; 1.244 Gbit/s; 768 kbit; ATM switch ASIC; data retention; embedded DRAM macrocell; high-bandwidth interface; p-channel 1T cell; queue memory; single-poly double-metal p-substrate n-well logic process; soft errors; Application specific integrated circuits; Asynchronous transfer mode; Clocks; Logic; Macrocell networks; Packaging; Random access memory; Semiconductor device measurement; Switches; Testing;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488615
