Aizup-a pipelined processor design and implementation on XILINX FPGA chip

Author

Li, Yamin ; Chu, Wanming

Author_Institution

Comput. Archit. Lab., Aizu Univ., Japan

fYear

1996

fDate

17-19 Apr 1996

Firstpage

98

Lastpage

106

Abstract

This paper describes a pipelined processor (named Aizup) design and implementation for the exercise of Computer Architecture/Organization Education at the University of Aizu. The Aizup, pipeline has four stages and deals with data dependency and control dependency. The Aizup was designed at Cadence environment and implemented on Xilinx XC4006PC84 FPGA chip. We ask students to design the processor, to perform functional simulations, to implement the design on the chip, and to measure the chip with logic analyzer. The exercise course is helpful to students to understand the operations of pipelined processors and to master the design methodologies and the use of measuring instruments

Keywords

computer science education; field programmable gate arrays; logic CAD; microprocessor chips; pipeline processing; Aizup; Cadence environment; XILINX FPGA chip; Xilinx XC4006PC84 FPGA chip; control dependency; data dependency; design methodologies; functional simulations; logic analyzer; measuring instruments; pipelined processor design; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-7548-9

Type

conf

DOI

10.1109/FPGA.1996.564755

Filename

564755