An FPGA-based digital class-D amplifier using short word-length

Author

Thakkar, Darshan ; Lethbridge, Geoffrey ; Targownik, Tomas ; Ling, Allen ; Sadik, Amin Z. ; Beckett, Paul ; Hussain, Zahir M.

Author_Institution

Sch. of Electr.&Comput. Eng., RMIT Univ., Melbourne, VIC

fYear

2007

fDate

2-5 Dec. 2007

Firstpage

293

Lastpage

297

Abstract

A digital Class-D amplifier based on single-bit processing to be implemented on a field programmable gate array (FPGA) is presented. The main focus of this design is the reduction of noise, a drawback of Class-D amplifiers, by exploring the noise-shaping characteristics of sigma-delta modulation (SDM). The audio signal is retained in the digital single-bit domain until the final stage of the amplifier, thus avoiding quantization noise due to conversion. This paper focuses on the SDM and digital signal processing (DSP) components of the design to be implemented on the FPGA.

Keywords

amplifiers; digital signal processing chips; field programmable gate arrays; interference suppression; sigma-delta modulation; DSP component; FPGA design; audio signal; digital class-D amplifier; digital signal processing; field programmable gate array; noise reduction; noise-shaping characteristics; sigma-delta modulation; single-bit processing; Delta-sigma modulation; Digital signal processing; Field programmable gate arrays; Multi-stage noise shaping; Noise reduction; Noise shaping; Pulse amplifiers; Pulse width modulation; Quantization; Space vector pulse width modulation; Class-D; FPGA; Sigma-Delta Modulation; VHDL;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunication Networks and Applications Conference, 2007. ATNAC 2007. Australasian

Conference_Location

Christchurch

Print_ISBN

978-1-4244-1557-1

Electronic_ISBN

978-1-4244-1558-8

Type

conf

DOI

10.1109/ATNAC.2007.4665278

Filename

4665278