Title :
Charge recycling differential logic for low-power application
Author :
Bai-Sun Kong ; Joo-Sun Choi ; Seog-Jun Lee ; Kwyro Lee
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Taejeon, South Korea
Abstract :
Energy efficiency has become one of the most important concerns in VLSI design. Conventional dynamic circuit techniques, which are preferred for high-speed operation, are inefficient as far as power consumption is concerned. Charge-recycling differential logic (CRDL) improves power efficiency by using some of the already-used charge for precharge. It has the benefit of improved noise margin due to inherently static operation.
Keywords :
MOS logic circuits; VLSI; adders; carry logic; integrated circuit design; integrated circuit noise; MOS logic; VLSI design; adders; charge recycling differential logic; energy efficiency; low-power application; noise margin; power consumption; power efficiency; precharge; static operation; Acceleration; CMOS logic circuits; Circuit noise; Clocks; Logic circuits; Logic devices; MOSFETs; Noise reduction; Recycling; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488628
