DocumentCode
3271298
Title
Power-efficient multiplier-accumulator design for FIR filters
Author
Farag, Emad N. ; Yan, Ran-Hong ; Elmasry, Mohamed I.
Author_Institution
Waterloo Univ., Ont., Canada
Volume
1
fYear
1997
fDate
25-28 May 1997
Firstpage
27
Abstract
Several low-power design techniques have been applied to the design of a power efficient multiplier-accumulator (MAC) array. The addition operation has been interleaved into the multiplier array. The MAC array is designed to have a programmable resolution so that the blocks corresponding to the least significant bits can be deactivated when a lower resolution is sufficient. The multiplier-accumulator has been designed in a 3.3 Volt 0.5 μm CMOS technology
Keywords
CMOS integrated circuits; FIR filters; multiplying circuits; 0.5 mum; 3.3 V; FIR filters; low-power design; multiplier array; multiplier-accumulator design; power efficient; programmable resolution; CMOS technology; Equations; Finite impulse response filter; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on
Conference_Location
St. Johns, Nfld.
ISSN
0840-7789
Print_ISBN
0-7803-3716-6
Type
conf
DOI
10.1109/CCECE.1997.614781
Filename
614781
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