Title :
Robust and energy-efficient DSP systems via output probability processing
Author :
Abdallah, Rami A. ; Shanbhag, Naresh R.
Author_Institution :
ECE Dept., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
Abstract :
This paper proposes to employ error statistics of nanoscale circuit fabrics to design robust energy-efficient digital signal processing (DSP) systems. Architectural level error statistics are exploited to generate probability or the reliability of each output bit of a DSP kernel. The proposed technique is referred to here as bit-level a posteriori probability processing (BLAPP). Energy efficiency and robustness of a 2D discrete cosine transform (2D-DCT) image codec employing BLAPP is studied. Simulations in a commercial 45 nm CMOS process show that BLAPP provides up to 14X improvement in robustness, and 25% power savings over conventional 2D-DCT codec design.
Keywords :
CMOS digital integrated circuits; codecs; digital signal processing chips; discrete cosine transforms; error statistics; image coding; integrated circuit design; probability; 2D discrete cosine transform image codec; CMOS process; DSP kernel; architectural level error statistics; bit-level a posteriori probability processing; energy efficient DSP system; nanoscale circuit fabrics; output probability processing; Complexity theory; Digital signal processing; Error analysis; Hardware; Kernel; Nuclear magnetic resonance; Robustness;
Conference_Titel :
Computer Design (ICCD), 2010 IEEE International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-8936-7
DOI :
10.1109/ICCD.2010.5647569