DocumentCode :
3271382
Title :
High throughput, low set-up time, reconfigurable linear Feedback Shift Registers
Author :
Nas, R.J.M. ; van Berkel, C.H.
Author_Institution :
ST-Ericsson, Eindhoven, Netherlands
fYear :
2010
fDate :
3-6 Oct. 2010
Firstpage :
31
Lastpage :
37
Abstract :
This paper presents a hardware design for a scalable, high throughput, configurable LFSR. High throughput is achieved by producing L consecutive outputs per clock cycle with a clock cycle period that, for practical cases, increases only logarithmically with the block size L and the length of the register N. Flexibility is ensured by offering full reconfigurability of the generator polynomial within 1 clock cycle. At the heart of the design is a decomposition of the block-based state-update transition-matrix into two matrices, which enables an efficient implementation in terms of both latency and area. Potential target applications for this design include PN sequence generation in CDMA systems, BIST for VLSI circuits, CRC, encryption and error correction.
Keywords :
VLSI; built-in self test; code division multiple access; cryptography; cyclic redundancy check codes; matrix algebra; shift registers; BIST; CDMA systems; CRC; PN sequence generation; VLSI circuits; block-based state-update transition-matrix; clock cycle period; encryption; error correction; high throughput; low set-up time; potential target applications; reconfigurable linear feedback shift registers; Clocks; Generators; Hardware; Mathematical model; Polynomials; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2010 IEEE International Conference on
Conference_Location :
Amsterdam
ISSN :
1063-6404
Print_ISBN :
978-1-4244-8936-7
Type :
conf
DOI :
10.1109/ICCD.2010.5647572
Filename :
5647572
Link To Document :
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