DocumentCode :
3271395
Title :
Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit
Author :
Arnold, Oliver ; Noethen, Benedikt ; Fettweis, Gerhard
Author_Institution :
Dept. of Mobile Commun. Syst., Dresden Univ. of Technol., Dresden, Germany
fYear :
2012
fDate :
19-21 Aug. 2012
Firstpage :
249
Lastpage :
254
Abstract :
In this paper a heterogeneous Multiprocessor System on-Chip (MPSoC) is controlled by a dynamic task scheduling unit called Core Manager. The instruction set architecture of this unit is extended to improve performance for dynamic data dependency checking, task scheduling, processing element (PE) allocation and data transfer management. In order to analyze and compare different implementations and trade-offs a tool flow was developed. Area and timing results are provided as well. A significant performance improvement can be shown for all parts of the Core Manager.
Keywords :
instruction sets; microprocessor chips; system-on-chip; CoreManager; MPSoC; PE allocation; data transfer management; dynamic data dependency checking; dynamic task scheduling unit; heterogeneous multiprocessor system on-chip; instruction set architecture extensions; processing element allocation; tool flow; Benchmark testing; Dynamic scheduling; Hardware; Program processors; Programming; dynamic task scheduling; heterogeneous MPSoC; instruction set extension;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
Conference_Location :
Amherst, MA
ISSN :
2159-3469
Print_ISBN :
978-1-4673-2234-8
Type :
conf
DOI :
10.1109/ISVLSI.2012.51
Filename :
6296481
Link To Document :
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