DocumentCode :
327154
Title :
A scaleable FIR filter using 32-bit floating-point complex arithmetic on a configurable computing machine
Author :
Walters, A. ; Athanas, Peter
Author_Institution :
Annapolis Micro Syst., MD, USA
fYear :
1998
fDate :
15-17 Apr 1998
Firstpage :
333
Lastpage :
334
Abstract :
This paper presents an approach for implementing a scalable high-performance digital filter using the WILDFORCE configurable computing platform. Although not designed specifically for signal processing, configurable computing platforms offer more flexibility for algorithms than application-specific hardware, which is often needed for instances when factors such as environment or product volume dictate alterations in computing. The added flexibility enables users to construct deep pipelines to exploit properties of specific computations. In this paper, wide 32-bit floating-point arithmetic operators have been implemented which provide compatibility with hosts machines. The filter achieves 160 MFLOPs on a single WILDFORCE configurable computing platform
Keywords :
FIR filters; digital filters; floating point arithmetic; signal processing; 32-bit floating-point complex arithmetic; WILDFORCE configurable computing platform; application-specific hardware; configurable computing machine; digital filter; scaleable FIR filter; signal processing; Computer architecture; Convolution; Filtering; Finite impulse response filter; Floating-point arithmetic; Pipeline processing; Signal design; Signal processing; Signal processing algorithms; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8900-5
Type :
conf
DOI :
10.1109/FPGA.1998.707941
Filename :
707941
Link To Document :
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