Computer design strategy for MCM-D/flip-chip technology

Author

Franzon, Paul D. ; Conte, Tayana ; Glaser, Axel ; Lipa, Steve

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC

fYear

1996

fDate

28-30 Oct 1996

Firstpage

6

Lastpage

8

Abstract

A compelling case is made for using MCM-D (thin film MultiChip Module) flip-chip technology to build a `MegaChip´ CPU consisting of an Instruction Fetch Unit and Execution Unit. By building part of the Instruction Fetch Unit in an optimized SRAM process, significant performance/cost gains are made. We also address the following important `implementation´: (1) Partitioning high speed paths across the chip boundary within timing specs; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; (4) Managing test costs; and (5) implementing a debug strategy. This paradigm is also potentially useful for other memory intensive applications, including ATM, etc

Keywords

flip-chip devices; integrated circuit packaging; microprocessor chips; multichip modules; timing; MCM-D/flip-chip technology; MegaChip CPU; chip boundary; clock distribution; debug strategy; execution unit; instruction fetch unit; optimized SRAM process; partitioning; test costs; thin film multichip module; timing specs;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting

Conference_Location

Napa, CA

Print_ISBN

0-7803-3514-7

Type

conf

DOI

10.1109/EPEP.1996.564758

Filename

564758