Title :
0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI
Author :
Watanabe, Takahiro ; Watanabe, Minoru
Author_Institution :
Electr. & Electron. Eng., Shizuoka Univ., Shizuoka, Japan
Abstract :
Currently, demand is increasing for high-speed dynamic reconfiguration on programmable devices to improve their performance. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been undergoing rapid development. Moreover, to more increase the reconfiguration speed, optically differential reconfigurable gate arrays (ODRGAs) incorporating a differential reconfiguration method between configuration contexts have been developed. An ODRGA comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Its large-bandwidth optical connection enables high-speed reconfiguration. However, photodiode sensitivities of conventional ODRGAs are not good. This paper therefore presents a newly fabricated 0.18 um CMOS process optically differential reconfigurable gate array VLSI chip with highly sensitive photo-circuits.
Keywords :
CMOS digital integrated circuits; VLSI; holography; laser arrays; logic arrays; programmable logic arrays; reconfigurable architectures; CMOS process; ODRGA; ORGA; configuration contexts; high-speed dynamic reconfiguration; holographic memory; large-bandwidth optical connection; laser array; photodiode sensitivities; programmable devices; reconfiguration speed; sensitive differential optically reconfigurable gate array VLSI chips; sensitive photo-circuits; IEEE Computer Society; Liquid crystal displays; Very large scale integration; Field Programmable Gate Arrays; Holographic memory; Optically reconfigurable gate arrays;
Conference_Titel :
VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
Conference_Location :
Amherst, MA
Print_ISBN :
978-1-4673-2234-8
DOI :
10.1109/ISVLSI.2012.71
