Title :
A dual floating point coprocessor with an FMAC architecture
Author :
Heikes, C. ; Colon-Bonet, G.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
The CPU chip is implemented in a 5-layer metal 0.5 /spl mu/m CMOS process and delivers >360 SPECint92 and >550 SPECfp92. It is an out-of-order super-scalar processor with two integer, two floating point, two shift/merge and two load/store units. This paper describes circuits in the floating-point unit of this CPU.
Keywords :
CMOS digital integrated circuits; coprocessors; floating point arithmetic; 0.5 micron; 5-layer metal CMOS process; CPU chip; FMAC architecture; dual floating point coprocessor; out-of-order super-scalar processor; Central Processing Unit; Circuit noise; Clocks; Coprocessors; Logic; Rails; Registers; Routing; Switches; Wires;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488714
