Title :
A sub-nanosecond 0.5 /spl mu/m 64 b adder design
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
A sub-nanosecond 64 b adder in 0.5 /spl mu/m CMOS forms the basis for the integer and floating point execution units. Integrating dual-rail dynamic CMOS and use of Ling´s equations, the adder is composed of 7k FETs in 0.246 mm/sup 2/ and performs a full 64 b add, operands to result in <1 ns (7 fanout of 4 inverter delays) under nominal conditions.
Keywords :
CMOS logic circuits; adders; floating point arithmetic; 0.5 micron; 64 bit; CMOS adder design; Ling equations; dual-rail dynamic CMOS; floating point execution unit; integer execution unit; subnanosecond adder; Adders; Circuits; Computer architecture; Delay; Equations; FETs; Hardware; Inverters; Logic; Rails;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488718
