DocumentCode
3271820
Title
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories
Author
Poremba, Matt ; Xie, Yuan
Author_Institution
Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA
fYear
2012
fDate
19-21 Aug. 2012
Firstpage
392
Lastpage
397
Abstract
Emerging non-volatile memory (NVM) technologies, such as PCRAM and STT-RAM, have demonstrated great potentials to be the candidates as replacement for DRAM-based main memory design for computer systems. It is important for computer architects to model such emerging memory technologies at the architecture level, to understand the benefits and limitations for better utilizing them to improve the performance/energy/reliability of future computing systems. In this paper, we introduce an architectural-level simulator called NV Main, which can model main memory design with both DRAM and emerging non-volatile memory technologies, and can facilitate designers to perform design space explorations utilizing these emerging memory technologies. We discuss design points of the simulator and provide validation of the model, along with case studies on using the tool for design space explorations.
Keywords
DRAM chips; circuit reliability; memory architecture; DRAM-based main memory design; NVM technologies; NVMain; architectural-level main memory simulator; architectural-level simulator; computer architecture; computer systems; design space explorations; main memory design; nonvolatile memories; Computational modeling; Delay; Integrated circuit modeling; Nonvolatile memory; Organizations; Random access memory; emerging memory technology; memory architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
Conference_Location
Amherst, MA
ISSN
2159-3469
Print_ISBN
978-1-4673-2234-8
Type
conf
DOI
10.1109/ISVLSI.2012.82
Filename
6296505
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