Author :
Saeki, T. ; Nakaoka, Y. ; Fujita, M. ; Tanaka, A. ; Nagata, K. ; Sakakibara, K. ; Matano, T. ; Hoshino, Y. ; Miyano, K. ; Isa, S. ; Kakehashi, E. ; Drynan, J.M. ; Komuro, M. ; Fukase, T. ; Iwasaki, H. ; Sekine, J. ; Igeta, M. ; Nakanishi, N. ; Itani, T. ;
Abstract :
A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.
Keywords :
DRAM chips; delays; memory architecture; pipeline processing; 2.5 ns; 250 MHz; 256 Mbit; SDRAM; cell-occupancy ratio array; clock access; first-in first-out buffer; parallel/serial converter; prefetched pipeline; synchronous mirror delay circuit; Clocks; Delay; Driver circuits; MOS devices; Mirrors; Phase locked loops; Pipelines; Prefetching; SDRAM; Systolic arrays;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
