HiperLAN 5.4 GHz low power CMOS synchronous oscillator

Author

Deval, Y. ; Begueret, J.-B. ; Spataro, A. ; Fouillat, P. ; Belot, D. ; Badets, F.

Author_Institution

IXL Lab., Talence, France

fYear

2001

fDate

20-22 May 2001

Firstpage

53

Lastpage

56

Abstract

A 5.4 GHz 0.25 /spl mu/m VLSI CMOS synchronous oscillator is proposed, which is designed to act as a local oscillator for HiperLAN systems. The design strategy is described, including the synchronization range optimization approach. A chip is presented, which provides a 150 MHz synchronization range and a -97 dBc/Hz phase noise at 10 kHz offset from the carrier, while only consuming 5 mA from a 2.5 V supply.

Keywords

CMOS analogue integrated circuits; MMIC oscillators; VLSI; circuit optimisation; integrated circuit design; synchronisation; wireless LAN; 0.25 micron; 2.5 V; 5 mA; 5.4 GHz; CMOS synchronous oscillator; HiperLAN system LO; VLSI CMOS oscillator; design strategy; local oscillator; low power oscillator; synchronization range optimization; Bandwidth; CMOS technology; Circuits; Design optimization; Frequency synchronization; Frequency synthesizers; Local oscillators; Phase locked loops; Phase noise; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2001. Digest of Papers. 2001 IEEE

Conference_Location

Phoenix, AZ, USA

ISSN

1529-2517

Print_ISBN

0-7803-6601-8

Type

conf

DOI

10.1109/RFIC.2001.935640

Filename

935640