3D CMOS SOI for high performance computing

Author

Aisa, P.A. ; Guyot, A. ; Courtois, B.

fYear

1998

fDate

10-12 Aug. 1998

Firstpage

54

Lastpage

58

Abstract

This paper addresses three topics : first, a new three-dimensional CMOS-SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. In this technology the P-channel devices are stacked over the N-channel ones. All gates are 100 nm length. New design constraints are introduced. Consequently, new design methodologies have to be developed in order to fully take advantage of the outstanding features of 3D integration, like for example the reduced length of interconnections. A 16/spl times/16 bit multiplier was designed in this technology. Comparative results between 2D and 3D integration are given here in terms of energy consumption, delay and area.

Keywords

CMOS digital integrated circuits; integrated circuit design; integrated circuit technology; multiplying circuits; silicon-on-insulator; 100 nm; 3D CMOS SOI technology; Si; delay; design methodologies; device area; energy consumption; high performance computing; multiplier; stacked P-channel devices; three-dimensional CMOS-SOI;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on

Conference_Location

Monterey, CA, USA

Print_ISBN

1-58113-059-7

Type

conf

Filename

708155