Title :
The impact of data characteristics and hardware topology on hardware selection for low power DSP
Author :
Keane, Gareth ; Spanier, Jonathan ; Woods, Roger
Author_Institution :
Sch. of Electr. Eng. & Comput. Eng., Queen´´s Univ., Belfast, UK
Abstract :
Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as carry-save array and Wallace tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill(TM) simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.
Keywords :
carry logic; circuit optimisation; circuit simulation; digital signal processing chips; integrated circuit interconnections; integrated circuit layout; low-power electronics; multiplying circuits; network routing; EPIC PowerMill simulations; Wallace tree multipliers; adders; carry-save array; data characteristics; data wordlengths; design flow; hardware selection; hardware topology; interconnect optimization; layout strategies; low power DSP systems; low power operation; multiplier structures; power consumption; routing optimization;
Conference_Titel :
Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
1-58113-059-7
