Title :
0.5 V CMOS logic delivering 200 million 8/spl times/8 bit multiplications/s at less than 100 fJ based on a 50 nm T-gate SOI technology
Author :
Dudek, Volker ; Grube, Reinhard ; Hofflinger, Bernd ; Schau, Michael
Author_Institution :
Inst. for Microelectron., Stuttgart, Germany
Abstract :
High-performance CMOS logic at a very low voltage of 0.5 V can deliver 150 million 8/spl times/8 multiplications/s at an energy level of only 30fJ, if 0.35 /spl mu/m SOI technology is enhanced with self-aligned 50 mm T-Gate transistors, if a new adder with a differential Manchester chain including special accelerators and if the DIGILOG multiplier, a leading-one-first pseudo-log multiplier with complexity order (n) are optimized simultaneously.
Keywords :
CMOS logic circuits; adders; low-power electronics; multiplying circuits; silicon-on-insulator; 0.35 micron; 0.5 V; 30 fJ; 50 nm; 8 bit; CMOS logic; DIGILOG multiplier; Si; T-gate SOI technology; adder; differential Manchester chain; energy level; leading-one-first pseudo-log multiplier; low voltage circuits; self-aligned T-Gate transistors;
Conference_Titel :
Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
1-58113-059-7
