Power dissipated by CMOS gates driving lossless transmission lines

Author

Ismail, Yehea I. ; Friedman, Eby G. ; Neves, Jose L.

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1998

fDate

10-12 Aug. 1998

Firstpage

139

Lastpage

141

Abstract

The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with AS/X simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. Therefore, the total power consumption is expected to decrease as inductance effects becomes more significant as compared to an RC model of the interconnect.

Keywords

CMOS logic circuits; integrated circuit interconnections; logic gates; low-power electronics; transmission line theory; CMOS gates; LC transmission line; RLC transmission line; dynamic power consumption; inductance effects; interconnect RC model; lossless transmission lines; short-circuit power consumption;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on

Conference_Location

Monterey, CA, USA

Print_ISBN

1-58113-059-7

Type

conf

Filename

708178