Selectors for high density crosspoint memory arrays: Design considerations, device implementations and some challenges ahead

Significant progress has been made in recent years in the research and development of Resistive RAM as future nonvolatile memory. To achieve even higher integration densities, the resistive switching element needs a two-terminal selector device, in a one-selector one-resistor (ISIR) serial cell, which enables suppression of the parasitic leakage paths in the memory array. In this paper, review a top-down approach to derive selector requirements, considering a worst-case crosspoint array model and resistive switching element characteristics. The requirements that a selector needs to meet are derived by systematic analysis of various bias schemes, considering a basic set of figures of merit, to describe array functionality and power efficiency. We furthermore briefly discuss several selector implementations to date, outlining their strengths and weaknesses. In the end, we point out selector variability impact on cell operation, which calls for even more stringent selector requirements to be met.