DocumentCode :
327254
Title :
Estimation of maximum power supply noise for deep sub-micron designs
Author :
Jiang, Yi-Min ; Cheng, Kwang-Ting ; Deng, An-Chang
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
1998
fDate :
10-12 Aug. 1998
Firstpage :
233
Lastpage :
238
Abstract :
We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the genetic algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.
Keywords :
circuit simulation; digital integrated circuits; estimation theory; genetic algorithms; integrated circuit design; integrated circuit modelling; integrated circuit noise; low-power electronics; 2-vector sequence; cell-level waveform simulator; charge/discharge current waveform library; circuit model; deep submicron designs; genetic algorithm; ground pin characteristics; maximum power supply noise estimation; output voltage waveform library; power net RC characteristics; power pin characteristics; transistor level simulator;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
1-58113-059-7
Type :
conf
Filename :
708194
Link To Document :
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