Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits

In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a V/sub dd/ close to V/sub T/ and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low V/sub dd/. To avoid reducing V/sub dd/ below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to V/sub T/ based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.