A low power SRAM using auto-backgate-controlled MT-CMOS

We have proposed a low power SRAM using an effective method called "ABC-MT-CMOS". It controls the backgates to reduce the leakage current when the SRAM is not activated (sleep mode) while retaining the data stored in the memory cells. We also adopted a "CSB Scheme" which clamps both the source lines of the memory cell array and the bit lines. We designed and fabricated test chips containing a 32 K-bit gate array SRAM. The experimental results show that the leakage current is reduced to 1/1000 in sleep mode. The active power is 0.27 mW/MHz at 1 V, which is a reduction of 1/12 of a conventional SRAM with a 3.3 V.