Title :
Lateral NWFET optimization for beyond 7nm nodes
Author :
Yakimets, D. ; Jang, D. ; Raghavan, P. ; Eneman, G. ; Mertens, H. ; Schuddinck, P. ; Mallik, A. ; Bardon, M. Garcia ; Collaert, N. ; Mercha, A. ; Verkest, D. ; Thean, A. ; De Meyer, K.
Author_Institution :
imec, Leuven, Belgium
Abstract :
In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must for lateral NWFETs in order to reduce device parasitic capacitance.
Keywords :
Ge-Si alloys; field effect transistors; nanowires; optimisation; semiconductor device models; DC oscillator levels; S-D contacting options; Si-SiGe; Si-SiGe super-lattice results; device parasitic capacitance; internal spacers; lateral NWFET devices; ring oscillator levels; Lattices; Logic gates; MOS devices; Performance evaluation; Silicon; Silicon germanium; Stress; Lateral gate-all-around FET; design technology co-optimization (DTCO); nanowire; scaling;
Conference_Titel :
IC Design & Technology (ICICDT), 2015 International Conference on
Conference_Location :
Leuven
DOI :
10.1109/ICICDT.2015.7165887
