An 8-Bit 250MSPS Modified Two-Step ADC

Author

Ning, Ning ; Fan, Long ; Wu, Shuang-yi ; Liu, Yuan ; Liu, Guo-qing ; Yu, Qi ; Yang, Mo-hua

Author_Institution

Sch. of Microelectron. & Solid-State Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu

Volume

4

fYear

2006

fDate

25-28 June 2006

Firstpage

2197

Lastpage

2200

Abstract

Based on conventional two-step ADC principle, an 8-bit 250MSPS modified two-step ADC is proposed to reduce power dissipation. It is realized by applying triple-stage comparison for the number reduction of comparators, substituting new reference region selecting logic (RRSL) blocks for sub-DACs and adding sample/hold (S/H) circuit to replace residue amplifier. Simulated with SMIC O.35 mum/3.3 V AMS Si-CMOS process models, the results are shown that on the condition of realizing 250MSPS, the ADC achieves DNL<plusmn0.4LSB, INL<plusmn.5LSB, SFDR 59.2 dB at Nyquist frequency, only 85 mW power dissipation and 1.2times0.8 mm² layout area. The ADC system architecture is to be employed in the field of high-speed low-power mixed-signal processing

Keywords

CMOS integrated circuits; analogue-digital conversion; silicon; AMS Si-CMOS process models; RRSL; mixed-signal processing; modified two-step ADC; reference region selecting logic; sample-hold circuit; Circuit simulation; Energy management; Feedback; Frequency; Logic circuits; Microelectronics; Power dissipation; Power system modeling; Solid state circuits; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems Proceedings, 2006 International Conference on

Conference_Location

Guilin

Print_ISBN

0-7803-9584-0

Electronic_ISBN

0-7803-9585-9

Type

conf

DOI

10.1109/ICCCAS.2006.285113

Filename

4064360