• DocumentCode
    3272760
  • Title

    Analysis of FPGA Logic Block Architectures and Functional Improvement of Fine Grained Cells

  • Author

    Zheng, Jun ; Ramnath, Rohith ; Jiang, Yingtao ; Yang, Mei

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV
  • Volume
    4
  • fYear
    2006
  • fDate
    25-28 June 2006
  • Firstpage
    2210
  • Lastpage
    2214
  • Abstract
    Up to date, many different FPGA logic block architectures, varying in size, functionality and complexity, have been proposed. The most common FPGA logic blocks either have multiplexers or look-up-tables (LUTs). This article evaluates the performance of logic block architectures of both kinds. For this purpose, logic cells from leading FPGA vendors are considered along with a few from the academia. A comparative study of number of logic cells required for a particular design, area occupied by a design, speed of implementation and utilization is performed. Based on this study, three novel fine grained logic block architectures have been proposed which show improved performance
  • Keywords
    field programmable gate arrays; multiplexing equipment; performance evaluation; table lookup; FPGA logic block architecture; fine grained cells; look up table; multiplexer; performance evaluation; Circuit testing; Computer architecture; Computer science; Educational institutions; Field programmable gate arrays; Logic design; Multiplexing; Propagation delay; Routing; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Circuits and Systems Proceedings, 2006 International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    0-7803-9584-0
  • Electronic_ISBN
    0-7803-9585-9
  • Type

    conf

  • DOI
    10.1109/ICCCAS.2006.285116
  • Filename
    4064363