Power-Gating Techniques for Low-Power Adiabatic Circuits

In adiabatic circuits, the energy dissipation occurs even for constant input signals, as output nodes are always charged and discharged by power-clocks during every cycle. Some adiabatic logic units can be switched off during idle periods to reduce energy loss. This paper presents a new power-gating technique for adiabatic circuits. A power-gating switch with bootstrapped NMOS transistors is used to detach adiabatic logic blocks from power-clocks. The CPAL (complementary pass-transistor adiabatic logic) circuits with the proposed power-gating technique are investigated. SPICE simulations show that energy loss is reduced greatly by shutting down idle adiabatic circuit blocks