Low Voltage Low Power Class-AB OTA with Negative Resistance Load

In this paper, a low voltage low power rail to rail class-AB OTA in standard CMOS technology is proposed. The architecture is based on current mirror OTA topology with a local feedback between the output nodes of the first stage. The negative resistance load (NRL) is employed for compensation parasitic resistance of the first stage and the DC gain of the proposed OTA is enhanced. Compared to conventional voltage controlled NRL circuit transistor sizing controlled NRL circuit is used to avoid negative voltage circuits in the proposed OTA. Class AB output stage is implemented to obtain rail to rail output swing and higher slew rate. Using a 0.18-mum standard CMOS process, the OTA has been designed to operate with IV supply voltage. For a load capacitance of 5 pf the proposed OTA achieves DC gain of 58.25 dB, GBW of 50 MHz, phase margin of 61 degrees, and slew rate of 2.3 v/muS with a quiescent power consumption of 67 muW