FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below

Author

Eneman, G. ; De Keersgieter, A. ; Mocuta, A. ; Collaert, N. ; Thean, A.

Author_Institution

Imec, Heverlee, Belgium

fYear

2015

fDate

1-3 June 2015

Firstpage

1

Lastpage

4

Abstract

This simulation work studies whether optimal wafer and channel orientations exist that maximize the mobility of 10 nm-node strained-silicon FinFETs. For NFinFETs, strain-relaxed buffers or source/drain stressors yield the highest mobilities on rotated-notch wafers. For PFinFETs, industry-standard directions give the highest mobilities when using Si_1-yC_y strain-relaxed buffers as a stress booster. Using {110} substrates leads to strained mobilities that are in between what can be obtained by industry-standard and rotated-notch directions.

Keywords

MOSFET; buffer circuits; semiconductor device models; stress-strain relations; FinFET stressor efficiency; NFinFET; PFinFET; channel orientations; industry-standard directions; optimal wafer orientations; rotated-notch wafers; size 10 nm; source-drain stressors; strain-relaxed buffers; strained mobilities; strained-silicon FinFET; stress booster; FinFETs; Industries; Sensitivity; Silicon; Standards; Stress; Substrates; FinFETs; Strain-Relaxed Buffers; TCAD; strain; stress;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2015 International Conference on

Conference_Location

Leuven

Type

conf

DOI

10.1109/ICICDT.2015.7165898

Filename

7165898