A Novel Technique for Improving the Linearity of MOS Sampling Switch

Author

Peng, Yunfeng ; Yan, Wei ; Kong, Derui ; Zhou, Feng

Author_Institution

ASIC & Syst. of State´´s Key Lab., Fudan Univ., Shanghai

Volume

4

fYear

2006

fDate

25-28 June 2006

Firstpage

2268

Lastpage

2272

Abstract

A novel technique is proposed to improve the linearity of the MOS sampling switch (SW) by generating a replica transistor with the same threshold voltage as the sampling transistor. And it is obtained by forcing the replica transistor to operate in the triode region with the help of resistive voltage divider. The circuit has been implemented in chartered 0.35 mum standard CMOS technology. The proposed switch achieves a spurious free dynamic range (SFDR) of 110 dB for a 30 MHz, 1 Vp-p input signal, sampled at a rate of 80 MS/s, about 10 dB over the conventional switch, and the on-resistance variation is reduced by 90%

Keywords

CMOS integrated circuits; VHF devices; triodes; voltage dividers; 0.35 micron; 1 V; 30 MHz; MOS SW linearity; SFDR; chartered 0.35 mum standard CMOS technology; replica transistor; resistive voltage divider; sampling switch; spurious free dynamic range; triode region; Application specific integrated circuits; CMOS technology; Dynamic range; Linearity; MOS devices; MOSFETs; Sampling methods; Switches; Switching circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems Proceedings, 2006 International Conference on

Conference_Location

Guilin

Print_ISBN

0-7803-9584-0

Electronic_ISBN

0-7803-9585-9

Type

conf

DOI

10.1109/ICCCAS.2006.285130

Filename

4064377