Interconnect Power Optimization Based on the Integration of High-level Synthesis and Floorplanning

In this paper, we mainly present a novel approach which is based on the integration of high-level synthesis (HLS) and floorplanning (FP), to solve the problem of optimizing interconnect power of circuit designs. Although many methods have been proposed to deal with the above problem either from the HLS part or from the FP part, none of them makes use of the interactive information between the two procedures to get a better optimization solution. Therefore, our proposed approach takes into account not only the physical information in HLS part, but also the behavioral information while in floorplanning. Experimental results on benchmarks indicate that our design can make an improvement on the total interconnect power dissipation by 15.4% over the original optimizing method