Title :
A pipelined VLSI chip architecture for real-time computed tomography of fan-beam data
Author :
Agi, Iskender ; Hurst, Paul J. ; Current, K. Wayne
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
Abstract :
Image reconstruction from projection data is very computationally intensive. A novel IC architecture is presented which can be used in a pipeline of identical ICs to reconstruct images from parallel- and fan-beam scanner configurations. The accuracy and the finite word-length effects of fan-beam reconstruction are considered. Software simulations of the architecture designed in a 1 μm CMOS technology show that a maximum clock speed of 40 MHz is possible under nominal operating conditions
Keywords :
CMOS integrated circuits; VLSI; computerised tomography; image reconstruction; medical image processing; parallel architectures; 1 micron; 40 MHz; CMOS technology; fan-beam data; fan-beam scanner configurations; finite word-length effects; image; maximum clock speed; pipelined VLSI chip architecture; real-time computed tomography; Attenuation; Computed tomography; Computer architecture; Detectors; Image reconstruction; Object detection; Pixel; Sensor arrays; Very large scale integration; X-ray imaging;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230165
