Low-Power and Low-Complextly Full Adder Design for Wireless Base Band Application

A novel full adder design with only 10 transistors is presented targeting low power arithmetic operation for wireless base band processing. To alleviate the multi threshold voltage loss and the speed degradation problems common in 10T full adder designs, an inverter is successfully embedded along the carry path at no extra circuit overhead. It helps restore the logic swing and thus the driving capability to enhance the speed of carry propagation. Post layout simulations in TSMC 2P4M 0.35-mum CMOS process model indicate that the proposed design outperforms in both speed and normalized power consumption aspects among peer 10T full adder designs. The performance edge becomes even bigger when the adders are cascaded for n-bit ripple carry addition. We further compare our design with other higher transistor count full adder designs. The simulations reveal that our design performs comparably well in speed and power metrics but enjoys the advantage of much lower circuit complexity