• DocumentCode
    3273295
  • Title

    Implementing Virtual Metrology into semiconductor production processes - an investment assessment

  • Author

    Koitzsch, Matthias ; Merhof, Jochen ; Michl, Markus ; Noll, Humbert ; Nemecek, Alexander ; Honold, Alfred ; Kleineidam, Gerhard ; Lebrecht, Holger

  • Author_Institution
    Fraunhofer IISB, Erlangen, Germany
  • fYear
    2011
  • fDate
    11-14 Dec. 2011
  • Firstpage
    2017
  • Lastpage
    2028
  • Abstract
    Continuously increasing complexity of semiconductor manufacturing processes drives the need for wafer to wafer and even within wafer control loops metrology. Applying Virtual Metrology (VM) techniques is one promising approach to reduce the time between process, measurement and corrective actions. Prior to implementation - besides technical aspects like testing - the investment into VM has to be assessed and justified on the basis of reliable and reasonable data. This paper presents the investment assessment for implementing VM algorithms into plasma etcher tools of a model semiconductor fabrication line. Core of the investment calculation is a spreadsheet-based calculation which allows for a results per quarter evaluation. A Discrete Event Simulation (DES) model was developed to produce relevant input data for the spreadsheet calculation. Potential risks - e.g., delivery of wrong VM results - due to the implementation of VM have been identified and evaluated using the standardized method of Failure Mode and Effects Analysis (FMEA).
  • Keywords
    discrete event simulation; etching; failure analysis; investment; production engineering computing; production equipment; semiconductor device manufacture; DES model; FMEA; VM algorithms; discrete event simulation; failure mode and effects analysis; integrated device manufacturers; investment assessment; plasma etcher tools; semiconductor fabrication line; semiconductor production processes; virtual metrology; wafer control loops metrology; Discrete event simulation; Investments; Metrology; Production facilities; Semiconductor device modeling; Semiconductor process modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation Conference (WSC), Proceedings of the 2011 Winter
  • Conference_Location
    Phoenix, AZ
  • ISSN
    0891-7736
  • Print_ISBN
    978-1-4577-2108-3
  • Electronic_ISBN
    0891-7736
  • Type

    conf

  • DOI
    10.1109/WSC.2011.6147915
  • Filename
    6147915