Optimal Wire Sizing for Early Stage Power/Ground Grid Planning

In this paper, we look at building robust on-chip power/ground (P/G) networks subject to limited routing resource, which becomes an important, yet challenging problem in nanometer VLSI design. We propose a novel method to size P/G wire widths of non-uniform P/G networks to minimize the worst-case static IR-drop. Our contributions consist of the following: (1) we propose an efficient worst-case IR-drop analysis method by exploiting the locality of C4-based P/G grids; (2) we formulate the optimal wire sizing of early-stage P/G planning as a nonlinear optimization problem. (3) We show the resulting problem is convex and can be solved by canonical math programming method effectively. Our proposed method is well suitable for P/G grid sizing at early-stage of P/G planning. Finally, experiment results show that the optimal sizing could be found in a few seconds, which validate the effectiveness of the proposed method