Floorplanning for Even On-Chip Thermal Distribution

In this paper, we present a floorplanning tool that aims at reducing hot spots and distributing temperature evenly cross a chip while optimizing the traditional design metric, chip area and total wire length. The floorplanning problem is represented by corner block list, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area, total wire length and temperature optimizations leading to a multi-objective optimization problem, solved using evolutionary annealing. The experimental results using MCNC benchmarks show that our combined area, wire length and thermal optimization technique decreases the maximal temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques, and no noticeable total wire length increase