Title :
Design guidelines for short, medium, and long on-chip interconnections
Author :
Deutsch, A. ; Becker, W.D. ; Katopis, G.A. ; Smith, H. ; Restle, P.J. ; Coteus, P.W. ; Surovic, C.W. ; Kopcsay, Gerard V. ; Rubin, B.J. ; Dunne, R.P. ; Gallo, T. ; Jenkins, Keith A. ; Terman, L.M. ; Dennard, R.H. ; Knebel, D.R.
Author_Institution :
Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY
Abstract :
Short, medium and long on-chip interconnections having line widths of 0.7-52 μm are being analyzed in five-metal-layer structures. Design guidelines are formulated for local and global wiring in order to achieve minimum delay and contain crosstalk. The regime when inductive effects are significant is explained and the importance of resistive losses in the power buses is highlighted. The trend in CMOS-based microprocessor chips is to include increasing amount of system functionality. The chip-to-chip interconnections need to be absorbed by the on-chip wiring. This is why five or more layers of metallization are now available or being planned and the wiring pitch is continually shrinking
Keywords :
CMOS digital integrated circuits; crosstalk; delays; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; microprocessor chips; wiring; 0.7 to 52 micron; CMOS-based microprocessor chips; crosstalk; delay; design guidelines; five-metal-layer structures; global wiring; inductive effects; line widths; local wiring; on-chip interconnections; on-chip wiring; power buses; resistive losses; system functionality; wiring pitch;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting
Conference_Location :
Napa, CA
Print_ISBN :
0-7803-3514-7
DOI :
10.1109/EPEP.1996.564768
