Low Stress Program and Single Wordline Erase Schemes for NAND Flash Memory

Voltage stress during programming is a major factor limiting reliability in NAND Flash memory. To control programming stress several desirable features such as random page program, partial page program, and low Vcc operation are eliminated or restricted. Program stress becomes more significant as process technology is scaled down and as single-level cell (SLC) gives way to multi-level cell (MLC) devices. To increase device reliability a low stress program scheme for random page program in SLC devices and a sequential program scheme for MLC devices is introduced. Separately, system-level performance degrades as a function of the NAND block size due to the additional operations necessitated by wear-leveling algorithms. Techniques for single wordline erase in SLC and partial block erase in MLC are introduced to minimize system overhead due to larger block size and to extend the system lifetime.