DocumentCode :
3273691
Title :
A Fast Data Structure for HPWL Based on Reusablity Analysis
Author :
Liu, Jiayi ; Dong, Sheqin ; Hong, Xianlong
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
Volume :
4
fYear :
2006
fDate :
25-28 June 2006
Firstpage :
2439
Lastpage :
2443
Abstract :
In the process of solution evaluation for simulated annealing, the computation for wire-length is still a time consuming part, though now the buffer planning and thermal model have taken up a lot of time. And the traditional wire-length model HPWL executes in O(ntimesm) time in which n stands for the number of nets and m is the average number of the modules that the nets connect. In order to reduce the time for HPWL calculation, we propose two new data structures in this paper: "Nets Union" and "Subset Chain" to handle two typical kinds of reusable nets information respectively that are "Complete Overlap" and "Partial Overlap". Then the HPWL calculation can be finished in O(alphantimesbetam),0<alpha,beta<1. And our experiment results show the effectiveness of our algorithm
Keywords :
data structures; integrated circuit modelling; integrated circuit technology; simulated annealing; HPWL; buffer planning; complete overlap; data structure; nets union; partial overlap; reusable nets information; simulated annealing; subset chain; thermal model; Analytical models; Computational modeling; Computer science; Data structures; Integrated circuit technology; Process design; Process planning; Simulated annealing; Transistors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems Proceedings, 2006 International Conference on
Conference_Location :
Guilin
Print_ISBN :
0-7803-9584-0
Electronic_ISBN :
0-7803-9585-9
Type :
conf
DOI :
10.1109/ICCCAS.2006.285169
Filename :
4064416
Link To Document :
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