Title :
Wiring rule methodology for on-chip interconnects
Author :
Smith, H. ; Cases, M.
Author_Institution :
IBM Corp., Poughkeepsie, NY
Abstract :
A wiring rule methodology which controls line to line signal coupling and transition rate degradations is described Technology trends are discussed and parametric curves presented which illuminate optimized wire geometries that are used to satisfy these electrical constraints for high wire density CMOS chips
Keywords :
CMOS integrated circuits; delays; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; timing; wiring; CMOS chips; electrical constraints; line to line signal coupling; on-chip interconnects; optimized wire geometries; parametric curves; technology trends; transition rate degradations; wire density; wiring rule methodology;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1996., IEEE 5th Topical Meeting
Conference_Location :
Napa, CA
Print_ISBN :
0-7803-3514-7
DOI :
10.1109/EPEP.1996.564769
