Use Augmented Connection Boxes to Improve FPGA Performance

With the rapid progress of VLSI technology FPGAs´ performance efficiency has become the main concern of designers and manufacturers. Our goal in this work is to propose a new FPGA structure to reduce critical net delay without increasing routing area. The augmented connection box is proposed. It allows two different signals to share one track in a connection box by inserting additional switches where logic pins have connection with tracks. The experimental results prove that the augmented connection box improves FPGAs´ delay performance by avoiding detour when nets are routed and the possible delay increase incurred by switch addition does not happen. Also channel width is reduced a lot