DocumentCode :
3273830
Title :
Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model
Author :
Fang, Shuai ; Huang, Zhangcai ; Kurokawa, Akira ; Inoue, Yasuaki
Author_Institution :
Graduate Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka
Volume :
4
fYear :
2006
fDate :
25-28 June 2006
Firstpage :
2474
Lastpage :
2477
Abstract :
Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to Ceff and RC-pi are not equal was not considered. With the progress of IC process technology, its influence on static timing analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation
Keywords :
capacitance measurement; integrated circuit design; integrated circuit interconnections; IC process technology; Spice simulation; Thevenin model; effective capacitance calculation; interconnect loads; Capacitance; Circuit simulation; Delay effects; Integrated circuit interconnections; Integrated circuit technology; Production systems; Semiconductor device modeling; Timing; Voltage; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems Proceedings, 2006 International Conference on
Conference_Location :
Guilin
Print_ISBN :
0-7803-9584-0
Electronic_ISBN :
0-7803-9585-9
Type :
conf
DOI :
10.1109/ICCCAS.2006.285176
Filename :
4064423
Link To Document :
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