DocumentCode :
3273837
Title :
Analysis and design of a low-power single-stage CMOS wireless receiver
Author :
Camponeschi, Matteo ; Bevilacqua, Andrea ; Andreani, Pietro
Author_Institution :
DEI, Univ. of Padova, Padova, Italy
fYear :
2009
fDate :
16-17 Nov. 2009
Firstpage :
1
Lastpage :
4
Abstract :
The thorough analysis and the design of a complete 2.2 GHz quadrature receiver front-end suited for low-power applications is reported in this work. The circuit, built in a 90 nm CMOS process, features a stacked single-ended low-noise amplifier and a self-oscillating mixer. The oscillator LC tank is designed to provide gain at low frequency without decreasing the quality factor at the oscillating frequency. A careful analysis shows that the parasitic capacitances at the output nodes ultimately limit the achievable conversion gain. Measurements show a conversion gain of 27.1 dB with a 14 MHz bandwidth, a noise figure ranging from 12.4 to 13.2 dB with a flicker corner frequency of 200 kHz and an input referred 1 dB compression point of -23.7 dBm. The circuit draws only 1.3 mA from a 1.0 V supply.
Keywords :
CMOS integrated circuits; radio receivers; bandwidth 14 MHz; current 1.3 mA; frequency 2.2 GHz; frequency 200 kHz; gain 12.4 dB to 13.2 dB; gain 27.1 dB; low-noise amplifier; low-power single-stage CMOS wireless receiver; oscillating frequency; quadrature receiver; self-oscillating mixer; voltage 1 V; CMOS process; Circuits; Frequency measurement; Gain measurement; Low-noise amplifiers; Mixers; Noise measurement; Oscillators; Parasitic capacitance; Q factor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP, 2009
Conference_Location :
Trondheim
Print_ISBN :
978-1-4244-4310-9
Electronic_ISBN :
978-1-4244-4311-6
Type :
conf
DOI :
10.1109/NORCHP.2009.5397826
Filename :
5397826
Link To Document :
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